I. Field of the Invention
This invention relates to a semiconductor device for use in a logic circuit prepared from integration of bipolar transistors, and more particularly to a semiconductor device of said type capable of being integrated with high density and operated with lower power consumption.
II. Description of the Prior Art
With a bipolar transistors-integrated semiconductor device, a separation layer for separating one element from another is necessary. This causes a process for manufacturing the semiconductor device to become complicated and simultaneously causes a rise of difficulties in integrating elements with high density. In order to solve this problem, an IIL-structural semiconductor device is being exploited which eliminates the necessity of providing such a separation layer and therefore makes high-density integration possible and yet operates with low power consumption.
A conventional IIL-structural semiconductor device, as well known, is constructed such that an n type epitaxial layer to serve as a base region or emitter region is formed on an n.sup.+ type silicon substrate to serve as a grounding region; in the n type epitaxial layer a p.sup.+ type layer used as a D.C. voltage supply region and a p type layer used as a signal input region are formed closely to each other; and in the p type layer at least one n.sup.+ type layer to serve as a signal output region is formed. An npn transistor operating as an inverter is constructed as a so-called inverted type transistor wherein the n type epitaxial layer, p type layer and n.sup.+ type layer are used as the emitter, base and collector, respectively, while a pnp transistor operating as an injector is constructed as a lateral transistor wherein the p.sup.+ type layer, n type epitaxial layer and p type layer are used as the emitter, base and collector, respectively.
The semiconductor device having the foregoing IIL structure has its npn transistor formed into an inverted structure to provide the advantages that a separation layer for separating one element from another is unnecessary; the degree of integration can be enhanced owing to the pnp and npn transistors co-owing two regions; and yet the logical amplitude and power consumption are both small or low.
However, the conventional IIL-structural semiconductor device still involves therein some problems. For example, the pnp transistor as an injector is of lateral type; and therefore the base width thereof fails to be narrowed to a sufficient extent, while the current amplification factor thereof is low. Further, the current flowing from the emitter in a vertical direction is consumed uselessly. In addition, the npn transistor as an inverter is formed into an inverted type, and therefore the current amplification factor thereof is also low and, since the base layer thereof is usually formed by diffusion, this base layer is applied with a decelerating field attributed to non-uniformity of impurity concentration.
The above-mentioned problems have heretofore been causes of interruption in making the IIL-structural semiconductor device into a type capable of reduction in power consumption and high-speed operation.
U.S. Pat. No. 3,823,353 discloses a monolithic semiconductor-integrated structure capable of being subjected to high-density integration and low in power consumption. This integrated structure has a semiconductor-integrated structure having disposed on a substrate of a first conductivity type a first layer of a second conductivity type, a second layer of said first conductivity type and a third layer of said second conductivity type in the order mentioned, and is constructed such that it is provided with a first region of said first conductivity type extended from the surface of said structure at least to the second layer in a manner to surround a specified region of the third layer, and with a second region of said second conductivity type extended from the surface of said structure to the first layer through the first region.